Many different types of integrated circuits and non-integrated circuits employ clock generating circuits such as phase lock loop circuits. Some examples of integrated circuits include, but are not limited to, graphics processors, central processing units, or any other suitable integrated circuits that employ clock generators. Manufacturing process variations, voltage supply variations and variations due to temperature changes, may cause a phase lock loop to go out of phase thereby causing clocked data to be lost (for example if the phase lock loop is the clock generator for a bus), or otherwise cause the lockup of other circuitry that depends upon a clock signal output by the phase lock loop circuit.
Although phase lock loop circuits employ a feedback structure that can adjust to, some degree, these variations, it can be difficult where for example a wide frequency range is desired. However, having a wide frequency range phase lock loop can also allow the introduction of noise since there is a wider frequency band. Accordingly, phase lock loop calibration circuits are known that attempt to calibrate the phase lock loop to calibrate an output signal to a suitable frequency range. However, these calibration circuits typically only operate during system resets or power ups.
FIG. 1 illustrates one example of such a known phase lock loop circuit 10 that employs discontinuous calibration, such as calibration upon reset but not during normal operation. As shown, a typical phase lock loop may include a phase detector 12 that receives a reference clock 14. The phase detector 12 outputs a difference in phase as a phase adjust signal 15 to a charge pump 16. The output of the charge pump 16 is a phase compensated signal 18 which is filtered by a low pass filter 20 before being applied to an analog adder 22. A controllable oscillator 24, such as a voltage controllable oscillator (VCO) receives a control signal output by the adder 22. The output of the controllable oscillator 24 is set at a desired frequency. A frequency divider 26 also receives an output frequency as part of a feedback loop L whose output is input to the phase detector 12.
The PLL circuit 10 compensates, for example for some level of process voltage and temperature (PVT) variations but may not be able to compensate enough depending on the structure of the PLL. To calibrate the PLL, firmware or other suitable logic detects a reset condition and the discontinuous calibration logic 30 sends a charge pump loop disable and reset calibration voltage signal 32 to cause the output of the charge pump 18 to be set to a fixed reference voltage through a suitable voltage divider network and switching array effectively disabling the feedback loop L. A digital-to-analog converter 34 also receives a calibration signal 36 which is output to an analog calibration signal 38 and serves as an input to the adder 22. As such, during reset conditions, the PLL is calibrated and then left to run freely during normal operations with no subsequent calibration. Although process variations due to voltage variations of the supply voltage and variations due to temperature may be compensated for the particular conditions during reset, the PLL circuit is not continuously calibrated during normal operation of the chip. Also the output voltage of the charge pump 16 can vary over time as well. The circuits 10 typically runs the voltage control oscillator through a range of settings using the calibration signal 38 and picks the best setting during reset. This is a feed forward approach. Moreover, if the PLL circuit serves as a clock generator for a data bus, address bus, control bus or any other bus, the bus typically must be in an idle condition so that data is not lost during the calibration procedure. For example, using the above technique, calibration cannot be done continuously because it requires the interruption of the feedback loop which would shut down a bus if the PLL circuit was continuously recalibrated.
Accordingly, a need exists to overcome one or more of the above limitations.